The present invention relates in general to semiconductor devices and, more particularly, to a method of forming a conductive structure (e.g., bit line) of a semiconductor device, which can reduce the resistance of the bit line.
A method employing a damascene process has been widely used as a method of forming a bit line of NAND flash memory. However, as the level of integration increases, the thickness and Final Inspection Critical Dimension (FICD) of the bit line decrease. Accordingly, problems occur, such as an abrupt decrease in the resistivity of the bit line. The causes of the problems are as follows:
1. As the height of the bit line decreases due to an increase of the level of integration, the resistivity of the bit line increases.
2. As the FICD of the bit line decreases because of an increase of the level of integration, the resistivity of the bit line increases.
3. In the case of Reactive Ion Etch (RIE), variation in resistance is very severe according to the profile of the bit line.
4. Due to at least the above three reasons, in the case where the damascene process of forming a bit line by gap-filling a trench with a bit line material (i.e., tungsten) is used, the weight of the barrier metal layer, which is formed before a primary bit line material (i.e., a tungsten layer) is deposited, is increased. Accordingly, the area occupied by the tungsten layer is limited and, therefore, it is difficult to reduce bit line resistance.